module div(clk,rst,clk_out);
input clk,rst;
output clk_out;
reg clk_out;
reg [8:0] cnt;
 
///////分频进程, 50Mhz 的时钟 326 分频/////////
always @(posedge clk)
begin
	if(!rst)
	begin
		clk_out<=0;  cnt<=4'd0;
	end
	else
	begin
	
	if(cnt==8'd162)
	begin
		clk_out<=~clk_out;
		cnt<=cnt+8'd1;
	end
	else if(cnt==8'd325)
	begin
		clk_out<=~clk_out;
		cnt<=8'd0;
	end
	else begin
		cnt<=cnt+16'd1;
	end
end
end
endmodule

